Leonardo Manuel Rocha

Hello Everybody, I've been working for the last year in studying a little bit about virtualization, and some month ago I started the design and development of a switch for embedding in a NIC that should do the switching function and virtualize NICs.

Why:

Well, now a days in 10GB Ethernet networks, the individual CPUs can not manage that much traffic. Some studies have shown that only is used 30% to 45% of available bandwidth, and that is because the incoming packets must be treated by only one processor that after filtering and different other tasks, can separate traffic.

In virtualized servers the situation is even worse, because the Hypervisor (or VMM) has to virtualize every NIC and generate a virtual switch with a virtual network that increases the overload of the CPU.

THe propose (and the ongoing work) is to create a NIC that has an embedded switch that not only does the switching task but also virtualize the NICS, so, the Hypervisor does not have to do this, and also we can distribute directly to the virtual machines (VMs) only the traffic that is for them and the processing tasks can be done in parallel (the different VMs can be over different CPUs).

At this moment I have a working input stage of the system programmed in SystemC but almost everything is in RTL, and one of the blocks already working in RTL in Verilog HDL (tested with Icarus Verilog).

The work is in progress at LCD (lcd.efn.unc.edu.ar with Jorge Manuel Finochietto as my Director and Mentor (he was the one with the idea, he is working in a high level simulator programmed with Omnet++) and I'm working in the architecture and low level implementation It has been a fabulous challenge and I really enjoyed it. Now I'm making some simulations and in a few weeks I hope having some interesting results.

As an advance in what will be shown to the public (I hope to show my design and some results to the public soon, there is being work done for writing a paper, and I hope some more will come later) I Attach the proposal I presented to the UNC (unc.edu.ar) FCEFyN (www.efn.unc.edu.ar) (where I study), but the beginings of this research comes from February/March. The attachment is in Spanish maybe later I will translate some.

When I'm ready I will share more information and also is my intention to publish the entire code, reports, results and tests under some licence that I'm still evaluating.
As an advance I publish also the architecture.

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